Jean Yves LeClerk studied under Dave Evans and upon getting his degree, went back to France. When he got an idea of how to build a supercomputer, he came back to Evans for advice on how to raise capital to fund the project. Evans said "I won't tell you how to raise money- I'll fund you myself." Thus, Evans & Sutherland got a computer division, ESCD. It was located in Mountain View, Ca, USA, just off US 101. Formed ca 1986, product shipped 1989, near midnight at the end of the September (so shipped in the quarter promised).
The building block was an 8 x 8 nonblocking crossbar, which could also connect to another similar crossbar without using one of the 8 x 8 connections. Use two crossbars to connect 16 processors to a memory system with 16 banks. Virtual memory, with translation done in the memory side of the crossbar (to allow faster context switches). The processor had a small TLB (512 ? page entries).
Use another 8 x 8 crossbar to connect 8 of those together, and you have 128 processors in one system. Note that this scheme may be extended: 8 128 processor systems could be connected by another 8 x 8 crossbar, etc. Great for data-parallel, too bad there wasn't any HPF in 1988 :-( (ESCD played around with PCF, IIRC) The system was a (theoretically) scalable shared memory NUMA computer.
ESCD had a unique nomenclature: the processors were called "computational units", and the set of 16 computational units and memory was called a "processor". Memory was 128 MB per "processor".
Use MACH for your OS, so you'll have a "parallel" unix. You need the parallel file system to drive the very good I/O subsystem, which was rated at 200 MB/s per processor (1.6 GB/s per full system).
Neatly finessing the issue of custom v. off-the-shelf processor, ESCD made their own processor, but used Weitek chips for the floating point. (This was back in the days when a processor was a "chip set", rather than the single die for sale today.) During development, the clock was 40 MHz, with plans to go to 50 Mhz by the time of production. 32-bit words, but the Weitek's would do 64-bit fp nicely. Luminal speed was about 12 Mflops per computatiuonal unit. Measured speeds (i.e., operands in memory rather than register) were more like 2-3 Mflops per.
There were some unexpected problems with the pipelines in the processors: certain instructions couldn't be issued at particular clocks after issue of certian other instructions. The French called this "pipeline hazards", the Californians called it "cursed instruction sequences". It was a closely guarded secret, and caused ESCD to not release the instruction set, nor the assembler.
Biggest problem with the design was memory access: processor to memory: return the physical address of this virtual address memory to processor: here's the paddress processor to memory: read/write data to/from this physical address memory to processor/processor to memory: here's the data
So a memory op was actually 4 messages rather than 2 anytime the physical address wasn't in the processor's small TLB. Think Linpack. 512 pages just ain't supercomputin'
Serials 1 and 2 went to Caltech and U. Colorado at Boulder (can't recall which got which). Up to about serial 7 or so were in some stage of production when the project ended. The ES-1 at CU Boulder was installed right beside, and during the same week as, the Myrias SPS-2. Head to head competition. (Myrias was in-and-out in a couple of days. ESCD needed a couple of weeks.)
Being within walking distance of Shoreline City Park, so a walk would clear the head of the frustrations of working on beta (alpha ?) HW & SW.
Culturally, ESCD couldn't take a meal together, because
The project ended when Evans resigned from the Board of E&S. Then a 4/3 vote in favor of the project became a 3/4 vote against. We got 60 days notice (U.S. plant closing law), it was announced at the Supercomputing convention in Reno. (If you have to end my project, end it at the Supercomputing convention. Most of the places I might look for work are within walking distance. For the record, Henry Cornelius was the first headhunter to our booth after the announcement, within 3 or 4 minutes.)
Don't push too many technologies simultaneously. Chips checked out on the silicon compiler, but were too dense (100K transistors in 1986) for the foundries to make at acceptable yield; MACH was not ready for commercial use in 1988.